The geometries of microelectronic features continue to scale to smaller sizes and increase in complexity. Accordingly, the patterning techniques used to manufacture microelectronic devices have become more precise to create smaller features and minimize damage to the films during manufacturing. Scaling to smaller light wavelengths for photolithography has been a successful approach to manufacture smaller devices. However, light wavelength scaling has reached some limitations that may be overcome by using sub-lithographic techniques such as multiple patterning (MP) or self-aligned double/quadruple patterning (SADP/SAQP). Although sub-lithographic techniques have extended device manufacturing to smaller geometries, they have also introduced processing complexity that may reduce device yield or increase manufacturing cost. The process complexity may include additional film layers that may need to be removed and reapplied to enable smaller device features. Incomplete removal of film layers may have a negative impact on sub-lithographic patterning. Hence, removing film layers to eliminate residual traces of overlying films on underlying films may improve patterning results. Accordingly, new processing techniques that may overcome the aforementioned issues may be desirable.